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308MHz/315MHz/418MHz/433.92MHz
Low-Power, FSK Superheterodyne Receiver
Numerous configurations can be used to generate the
data-slicer threshold. For example, the circuit in Figure 3
shows a simple method using only one resistor and one
capacitor. This configuration averages the analog out-
put of the filter and sets the threshold to approximately
50% of that amplitude. With this configuration, the
threshold automatically adjusts as the analog signal
varies, minimizing the possibility for errors in the digital
MAX7042
DATA
SLICER
data. The values of R and C affect how fast the thresh-
old tracks the analog amplitude. Be sure to keep the
DATA
DS-
R
DS+
corner frequency of the RC circuit much lower than the
lowest expected data rate.
With this configuration, a long string of zeros or ones
can cause the threshold to drift. This configuration
works best if a coding scheme, such as Manchester
coding, which has an equal number of zeros and ones,
is used.
Figure 4 shows a configuration that uses the positive and
negative peak detectors to generate the threshold. This
configuration sets the threshold to the midpoint between
a high output and a low output of the data filter.
C
Figure 3. Generating Data-Slicer Threshold
MAX7042
Peak Detectors
The maximum peak detector (PDMAX) and minimum
DATA
SLICER
PEAK
DET
PEAK
DET
peak detector (PDMIN) outputs, in conjunction with a
resistor and capacitor connected to GND, create DC
output voltages proportional to the high- and low-peak
values of the data signal. The resistor provides a path
for the capacitor to discharge, allowing the peak detec-
DATA
PDMAX
R
R
PDMIN
tor to dynamically follow peak changes of the data-filter
output voltage.
The positive and negative peak detectors can be used
C
C
together to form a data-slicer threshold voltage at a
midvalue between the most positive and most negative
voltage levels of the data stream (see the Data Slicers
section and Figure 4). Set the RC time constant of the
peak-detector combining network to at least 5 times the
data period.
The MAX7042 peak detectors track the baseband filter
output voltage until all internal circuits are stable follow-
ing an enable pin low-to-high transition. This feature
allows for an extremely fast startup because the peak
detectors never “catch” a false level created by a startup
transient. The peak detectors exhibit a fast-attack/slow-
decay response.
Power-Supply Connections
The MAX7042 can be powered from a 2.4V to 3.6V
supply or a 4.5V to 5.5V supply. The device has an on-
chip linear regulator that reduces the 5V supply to 3V
needed to operate the chip.
Figure 4. Generating Data-Slicer Threshold Using the Peak
Detectors
To operate the MAX7042 from a 3V supply, connect
DVDD, AVDD, and HVIN to the 3V supply. When using
a 5V supply, connect the supply to HVIN only, and con-
nect AVDD to DVDD. In both cases, bypass DVDD and
HVIN with a 0.01μF capacitor and AVDD with a 0.1μF
capacitor. Place all bypass capacitors as close to the
respective supply pin as possible.
Control Interface Considerations
When operating the MAX7042 with a +4.5V to +5.5V
supply voltage, the LNASEL, FSEL1, FSEL2, and EN
pins can be driven by a microcontroller with either 3V
or 5V interface logic levels. When operating the
MAX7042 with a +2.4V to +3.6V supply, the microcon-
troller must produce logic levels tha conform to the V IH
and V IL specifications in the DC Electrical
Characteristics Table.
14
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